The present invention relates to controlling the timing of a clock signal in high speed circuits, such as an analogue-digital converter (ADC).
High speed data transfer between semiconductor devices in an electronic system may be achieved by the use of a serialiser/deserialiser (SerDes). In order to avoid the use of a plurality of parallel connections between devices, a single differential analogue path is used running at a high data rate. One exemplary arrangement is specified by IEEE 802.3/AE/P.
In some high speed data transfer techniques, the incoming data is latched using a clock signal. Often, the delay between the incoming data being clocked into the circuit and being ready to use (referred to as the “clock-to-Q period”) is large enough to cause problems. In particular, the clock-to-Q period may be sufficient to result in the original clock signal being inappropriate to clock the latched signal. Furthermore, the clock-to-Q period is typically process dependent and is often difficult to predict. It has proved to be difficult to provide clock signal timing in such circuits.